Recientemente under the mantle of the Linux Foundation a new project was formed, the CHIPS Alliance "Common Hardware for Interfaces, Processors and Systems"(Common hardware for interfaces, processors and systems), intended to promote open hardware systems and develop solutions based on the RISC-V architecture.
The founders of this new project "CHIPS Alliance" they are Google, SiFive, Western Digital and Esperanto Technologies. CHIPS Alliance is destined to position itself as a neutral and independent platform.
What is the CHIPS Alliance?
This platform will allow various equipment manufacturers (hardware) can develop their projects together to create open CPU out-of-the-box implementations and single chip systems (SoC) using the RISC-V architecture.
RISC-V (pronounced "Risk-Five") is a free hardware instruction set architecture (ISA) based on a RISC-like design. Unlike most instruction sets, RISC-V's is free and open and can be used for any purpose.
Allowing anyone to design, manufacture and sell RISC-V chips and software. While it is not the first open architecture ISA, but it is significant because it is designed to be useful on a wide range of devices.
Though currently the organization of the RISC-V Foundation deals only with architecture from the instruction set, but it does not deal with specific implementations.
That is why this new foundation was born and the task of the CHIPS Alliance is to prepare a standard open chip design for mobile devices, computer systems, consumer electronics and the Internet of things.
"Open collaboration has repeatedly been shown to help industries accelerate time to market, achieve long-term maintenance, and create de facto standards," said Mike Dolan, vice president of strategic programs for the Linux Foundation. "
As your initial contribution, the founders of the CHIPS Alliance presented the following projects for joint development.
SweRV Core
This is a 32-bit RISC-V processor developed by Western Digital. The chip operates at a frequency of 1,8 GHz, It is built on an architecture with 8-level dual trunk pipelines (2-way superscale) and is designed for production using 28nm CMOS process technology.
Schematics, documentation, CAD models, chip design, microcode, and full implementation in the Verilog language are open under the Apache 2.0 license.
OmniXtend
Es a network protocol that provides cache consistency when transferring data over Ethernet.
OmniXtend will allows you to exchange messages directly with the processor cache and can be used to connect various accelerators, storage devices, memory devices (NVDIMMs) and network interfaces to the SoC, as well as to create systems with multiple RISC-V chips. Project transferred by Western Digital.
UVM
Google has transferred the implementation of the Universal Verification Methodology (UVM) for stress testing RISC-V computing elements and design tools.
In particular, we are talking about a customizable instruction flow generator, which can be used to identify flaws and bottlenecks at the architecture and microarchitecture level.
About us YesFive, founded by the creators of RISC-V they prepared the first prototype of a processor based on RISC-V, in addition to creating a new hardware description language Chisel together with UC Berkeley.
Will transfer the RocketChip SoC generator to the project, the initial release of the consistent TileLink interface to link SoC components and the Diplomacy framework.
As part of the joint project, SiFive will also continue the development of the Chisel language and the interim presentation of the FIRRTL.
Currently, Based on the RISC-V specification, different companies and communities under various free licenses (BSD, MIT, Apache 2.0) are developing 21 variants of microprocessor cores:
10 SoCs and 6 chips already commercially available (SiFive FE310-G000, SiFive Freedom U540, GreenWaves GAP 8, Kendryte K210, NXP RV32M1 and RavenRV32).
Support for RISC-V has been around since the releases of Glibc 2.27, binutils 2.30, gcc 7, and the Linux kernel 4.15.
Source: https://www.linuxfoundation.org