In the past week An announcement was made by W. Clifford who released the new version 0.8 of Yosys.
For those who have not heard about Yosys I can tell you that eThis is a framework for RTL synthesis tools. Currently counts with broad Verilog compatibility and provides a basic set of synthesis algorithms for various application domains.
Many things have been added in this new release, but the main information that can be seen in the release note is that the development of Yosys is very active.
Yosys's goal of becoming the FPGA's "free Swiss Army knife" can be considered almost indispensable today.
Table of Contents
About Yosys Open SYnthesis Suite
yosys can be adapted to perform any synthesis work by combining existing passes (algorithms) using synthesis scripts and adding additional passes as needed when extending the Yosys C ++ codebase.
Yosys is free software licensed under the ISC license (a GPL-compliant license that is similar in terms to the MIT license or the 2-clause BSD license).
In the FPGA / ASIC development process, synthesis is the step of converting the simulated hardware model to "RTL netlist" from which the actual circuit can be derived.
verilog is a Hardware Modeling Language (Hardware Description Language HDL) for describing a simulation of digital circuits.
This Verilog model serves as a specification for a "physical" realization of the modeled component.
HDL synthesis can be viewed as a conversion of the HDL code into an "electronic scheme" consisting of digital components connected together. This is called the "RTL Network List" (Log Transfer Level).
Yosys is not the only free software for Verilog synthesis (We can also think of using ODIN II in the VTR software suite).
But, without a doubt, free software is the one that has been talked about the most recently and whose development is the most active.
In fact, Yosys now targets a lot of cheap FPGAs like CoolRunner-II, ECP5, MAX10, Cyclone IV and especially the ICE40.
The ICE40 is a bit special on the list, as for this FPGA the entire development chain has been launched.
Of course, we can do Verilog synthesis since the FPGA is compatible with Yosys, but also the routing location with arachnepnr, as well as the generation of the configuration file (bitstream) with icepack / iceprog.
It is also possible to check the times with icetime.
About the new version of Yosys
- In this new Yosys launch, the new functionalities have been announced, of which the following can be highlighted:
- The FIRRTL language used by Chisel3 is a possible backend to generate the netlist;
- The support of the formal verification engine of yosys-smtb can almost be considered stable.
- The list of supported FPGAs (and other ASICs) is hopelessly long;
- As well as the «netlist» formats that allow re-integration into the founders' proprietary software: BLIF, EDIF, BTOR, SMT-LIB, RTL Verilog, FIRRTL
How to install Yosys on Linux?
For whom it is are interested in being able to try this tool, they can perform the installation on their systems. To do this, they must follow the instructions that we share below.
For, those who are Ubuntu users and derivatives of it can enjoy a simple installation. This can be done by adding the following repository to your system.
First we must open a terminal with Ctrl + ALT + T and in it execute the following command:
sudo add-apt-repository ppa:saltmakrell/ppa
Done this now we must update our list of packages and repositories with:
sudo apt-get update
And finally we install the application with:
sudo apt-get install yosys
For the rest of the Linux distributions we must compile the tool. For this we must clone the source code of the GIT repository:
git clone https://github.com/cliffordwolf/yosys.git
Configure build settings with:
make config-clang vi Makefile vi Makefile.conf
Finally build, test and install:
make make test sudo make install
In order to obtain more information about it, as well as to be able to find documentation on the use of Yosys, you can visit the following link.