VRS and CacheOut, two new vulnerabilities that affect Intel

Recientemente Intel revealed two new vulnerabilities in its own processors, once again refers to variants from the well-known MDS (Microarchitectural Data Sampling) and are based on the application of third-party analysis methods to data in microarchitecture structures. The researchers from the University of Michigan and the Vrije Universiteit Amsterdam (VUSec) they discovered the possibilities of attack.

According to Intel, this affects current desktop and mobile processors such as Amber Lake, Kaby Lake, Coffee Lake, and Whiskey Lake, but also Cascade Lake for servers.

Cache Out

The first of them has the name L1D Eviction Sampling or L1DES for short or it is also known as CacheOut, registered as "CVE-2020-0549" this is the one with the greatest danger since allows sinking of cache line blocks forced out of the first level cache (L1D) in the fill buffer, which should be empty at this stage.

To determine the data that has settled into the padding buffer, the third-party analysis methods previously proposed in the MDS and TAA (Transactional Asynchronous Abort) attacks are applicable.

The essence of the previously implemented protection of MDS and TAA turned out that, under some conditions, the data is speculatively flushed after the cleanup operation, thus the MDS and TAA methods are still applicable.

As a result, an attacker can determine whether the data that has been moved from the top-level cache during the execution of an application that previously occupied the core of the current CPU or applications that simultaneously execute in other logical threads (hyperthread) in the same CPU core (disabling HyperThreading inefficiently reduces the attack).

Unlike the L1TF attack, L1DES does not allow to select specific physical addresses for verification, but allows passive monitoring of activity in other logical sequences associated with loading or storing values ​​in memory.

The VUSec team adapted the RIDL attack method for the L1DES vulnerability and that an exploit prototype is also available, which also bypasses the MDS protection method proposed by Intel, based on the use of the VERW instruction to clear the content of the microarchitecture buffers when they return from the kernel to user space or when they transfer control to the guest system.

On the other hand, also ZombieLoad has updated its attack method with the L1DES vulnerability.

While researchers at the University of Michigan have developed their own attack method CacheOut that allows you to extract sensitive information from the operating system kernel, virtual machines and SGX secure enclaves. The method relies on manipulations with the TAA to determine the contents of the fill buffer after the data leak from the L1D cache.

VRS

The second vulnerability is Vector Register Sampling (VRS) a variant of RIDL (Rogue In-Flight Data Load), which is related to a Store Buffer leak of the results of the vector register read operations that were modified during the execution of the vector instructions (SSE, AVX, AVX-512) on the same CPU core.

A leak occurs in a rather rare set of circumstances and it is caused by the fact that a speculative operation performed, leading to the reflection of the state of the vector records in the storage buffer, is delayed and terminated after the buffer is cleared, and not before. Similar to the L1DES vulnerability, the contents of the storage buffer can be determined using MDS and TAA attack methods.

However, according to Intel unlikely to be exploitable since it lists it as too complex to carry out real attacks and assigned a minimum level of danger, with a CVSS score of 2.8.

Although the researchers of the VUSec group have prepared an exploit prototype that allows you to determine the values ​​of the vector registers obtained as a result of calculations in another logical sequence of the same CPU core.

CacheOut is particularly relevant for cloud operators, as attack processes can read data beyond a virtual machine.

Finally Intel promises to release a firmware update with the implementation of mechanisms to block these problems.


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