UCIe, an open standard for chiplets

Few days ago made himself known he announced the formation of the UCIe consortium (Universal Chiplet Interconnect Express), whose goal is to develop open specifications and form an ecosystem for chiplet technology.

Intel, AMD, ARM, Qualcomm, Samsung, ASE (Advanced Semiconductor Engineering), Google Cloud, Meta/Facebook, Microsoft and Taiwan Semiconductor Manufacturing Company have joined the chiplet technology initiative.

The open specification UCIe 1.0, which standardizes methods for connecting integrated circuits on a common base, protocol stack, software model, and test process, is brought to public attention. Of the interfaces for connecting chipsets, support for PCIe (PCI Express) and CXL (Compute Express Link) is announced.

chiplets allow to create combined hybrid integrated circuits (multi-chip modules) made up of independent semiconductor blocks that are not tied to a manufacturer and interface with each other via a standard high-speed UCIe interface.

To develop a specialized solution, for example creating a processor with a built-in accelerator for machine learning or network operations processing, when using UCIe, it is sufficient to use existing chipsets with processor cores or accelerators offered by different manufacturers.

If there are no standard solutions, you can create your own chiplet with the necessary functionality, using technologies and solutions that are convenient for you.

“AMD is proud to continue its long tradition of supporting industry standards that enable innovative solutions to meet the changing needs of our customers. We have been a leader in chiplet technology and welcome a multivendor chiplet ecosystem to enable customizable third-party integration,” said Mark Papermaster, executive vice president and chief technical officer, AMD. “The UCIe standard will be a key factor in stimulating system innovation by relying on heterogeneous calculation engines and accelerators that will allow obtaining the best optimized solutions in terms of performance, cost and energy efficiency. »

Thereafter, it is enough to combine the selected chips using a design of blocks in the style of LEGO builders (The proposed technology is somewhat reminiscent of the use of PCIe boards to compose the filler of a computer, but only at the level of integrated circuits). Data exchange and interaction between the chipsets is carried out through a UCIe interface high speed, and the system-on-package (SoP) paradigm is used for the design of the blocks instead of the system-on-chip (SoC, system-on-chip).

Compared to SoCs, chiplet technology makes it possible to create reusable and replaceable semiconductor blocks that can be used in different devices, significantly reducing the cost of chip development.

Chiplet-based systems can combine different architectures and manufacturing processes; Since each chiplet works separately, interfacing through standard interfaces, blocks with different instruction set architectures (ISAs), such as RISC-V, ARM, and x86, can be combined into a single product. The use of chiplets also simplifies testing: each chiplet can be tested separately at the stage before integration into a ready-made solution.

Cheolmin Park, vice president of memory product planning teamof Samsung Electronics, said:

“Samsung anticipates that chiplet technology will be needed to improve the performance of computing systems as compute nodes continue to evolve, with the arrays within each cabinet possibly communicating via a single language.

We hope that the UCIe consortium will foster a vibrant chiplet ecosystem and establish a viable, open standard, industry-wide interface framework. As a comprehensive provider of foundry, logic, and memory solutions, Samsung plans to lead the consortium's efforts to further identify the best ways to improve system performance using chiplet technology."

Finally, if you are interested in knowing more about it, you can consult the details in the following link.


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