Si Europe is already creating its own general-purpose microprocessor with its EPI project, India is not idle. There have already been several attempts like these, such as the famous Russian Elbrus. I don't know if you remember it, a Russian microprocessor based on SPARC. But now things are much more serious, and these new designs that are emerging have a very powerful and good ISA to work on and build the microarchitecture on. I mean RISC-V.
Now India also has a microprocessor Made in India. It's called Shatki and you can see more information on the official website, but it seems like a very interesting project. And if expectations are met, we could have it on PCs soon, competing with Intel and AMD chips, but with cheaper prices. In terms of performance, we'll see, but for the moment, all these new projects are not simply intended to be low-cost alternatives with low returns, but rather to be powerful.
The example is EPI, which will also be used for supercomputers. In the case of Shatki, the processor of India, it's ready and the Indian Institute of Technology (IIT) Madras has released a software development kit for it. The SDK will allow developers to create apps for this chip based on the ISA RISC-V.
The Shatki chip was funded by the Ministry of Electronics and Information Technology of India, something similar to what they have done here in Europe, which is a collaborative project funded by the EU. In India it seems that they are also following these same steps. The group that has been in charge of its development is RISE from IIT and they have been working on it since 2016.
El plan is to launch 6 classes of processors. Each will have a different target or market for its performance characteristics and power consumption. China, India and Europe are already working hard for the non-dependence of the United States, and this complicates things for current designers such as Intel and AMD.
They are not really being commercialized at the moment, but with the SDK out, developers can already create software before it is even released. But it is not a rumor far from it, nor do you expect that it will take many years. The launch will take place in the near future and the thing is quite serious.
Like the European EPI, which will also be destined for various sectors, such as supercomputing, low consumption, automotive and for consumer computing, the case of Shatki is similar with several well-known classes. If you want know the classes of this microprocessor are:
- Class e: it is a processor aimed at embedded or embedded devices, such as small IoT devices, robotic platforms, motor controllers, industrial use, etc. It will compete against small microcontroller chips.
- C class: It is a 32-bit microcontroller with 5 stages, compared to 3 in the previous one. IN this case, it supports speeds from 200 Mhz to 1Ghz. It is aimed at mid-range application workloads and has a low power consumption profile, as well as support for memory protection. It will compete with microcontrollers and some low-power chips.
- Class I: it is a processor with out-of-order execution and speeds between 1.5 and 2.5 Ghz with multithreading. In this case, it is intended to be used for mobile devices and network applications such as routers, etc. It will compete with the ARMs.
- Clase m: It is another more powerful processor or series with multicore and shares characteristics with the Class I. It will have more than 8 processing cores, therefore, aimed at applications that demand more performance. In this case, for PCs. It could compete with the AMD Ryzen and Intel Core.
- Lessons: Shakti S Class is intended for workstations and servers. It is an improved version of the Class I. It is the alternative to the Xeon or EPYC, although the performance is still unknown.
- Class H: It is the highest performance processor of all, destined for supercomputing. One of its main functions is to include a high performance single-thread, L4 cache, and technologies to improve I / O performance in the HPC field.
- Experimental classes: RISE is also working on two new classes in the experimentation phase at the moment. These are class T and class F. In this case, the first will be optimized for better security (overflow prevention, attack mitigation, ...), and the second aimed at improving class T with support for ECC memory.
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