A group of enthusiasts (with contributions from Pixilica) are developing the project RV64X, which aims to create a set of supplemental 3D graphics and multimedia processing instructions that can be used to integrate the functionality of the GPU on RISC-V processors.
Pixilica partners with RV64X to propose a new set of graphics instructions designed for 3D graphics and media processing. It may be a fused ISA CPU-GPU.
These new instructions are based on the RISC-V base vector instruction set. They will add support for new data types that are graphics specific as layered extensions in the spirit of the RISC-V ISA kernel.
RV64X is based on RISC-V ISA vector instructions, which are enhanced with support for new data types and chart-specific extensions.
For example, additional operations are proposed for processing pixels (RGBA), dots (xyzw), texture elements (UVW-Texels), vectors (operations with 2-4 elements), material parameters, lighting calculations , transcendental mathematics, depth buffers (Z - buffer) and frame buffer (Framebuffer).
The first prototype RV64X-based GPU is designed for use in microcontrollers and will be limited to support for the Vulkan graphics API, although over time, they promise to add support for OpenGL and DirectX.
The main motivation for development is the need for a flexible architecture that allows connecting extensions to efficiently solve specific problems, such as two-phase truncation of cones, use of fast Fourier transforms for arbitrary color depths, and implementation of SLAM hardware.
For example, RV64X allows the implementation of its own stages for the computational pipeline, geometric, pixel and frame buffers, as well as creating your own tessellators.
It is also mentioned that with RV64X, chip manufacturers will be able to prepare the solutions they need based on the existing backbone, focusing on advanced capabilities, without having to waste time on common things.
RV64X is evolving as a hybrid CPU-GPU ISA, allowing the creation of specialized graphics microcontrollers and multicore processors that combine computational cores with blocks to perform graphical operations.
A processor that combines a RISC-V core with a GPU block looks like a single unit (no explicit GPU mapping) and is programmed using a unified 64-bit instruction set and SIMD model for data layer parallelism. The RV64X architecture is evolving towards a compact and efficient implementation that can be implemented on the basis of FPGAs and ASICs.
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Among the features of RV64X architecture the use of a single memory model is found on the CPU and GPU, which eliminates additional RPC / IPC mechanisms to translate calls between the GPU memory and the CPU when processing 3D API operations.
Standard graphics operations can be implemented at the microcode level. Creating custom shaders, rasterizers, and ray tracing extensions is supported. Additionally, vector operations can be implemented at the microcode level to solve simulation, computer vision, and machine learning problems.
The reference implementation RV64X includes 1 KB L32 cache for instructions and data, 8 KB SRAM for microcode, instruction decoder, hardware implementation of RV32V and RV64X instruction sets, microcode-defined extended instruction decoder, vector arithmetic logic unit (ALU), 136-bit register file with 1024 elements, a Special Function Unit (SFU), a Texture Unit and a configurable local framebuffer.
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