QEMU 6.2: RISC-V, SGX, Apple Silicon (M1) and more ...

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As you know, QEMU is a great open source project that acts as an emulator for different architectures. For its operation, it uses the dynamic translation of binaries, in addition to having virtualization capabilities to be able to run systems and software from other platforms (x86, ARM, SPARC, RISC-V, PPC,…). Now comes version 6.2, and it has very important advances.

QEMU 6.2 is on the way with support for Intel's SGX in virtual machines, which is interesting for security. It will also come with support enhancements for Apple Silicon (M1, M1 Pro, M1 Max), as well as the new and emerging ISA RISC-V. These are big words, and great news for users who use this software for emulation.

A few days ago it was launched QEMU 6.2-rc0, that is, the first candidate for a final version (Release Candidate) and that can already be tested to verify all these updates and if it works correctly. From there, new candidates have been released every week until it is ready and marked as QEMU 6.2.0 stable, which should be mid-December if there are no delays or issues in development.
In addition, some corrections will also arrive with respect to previous versions, and many others improvements:

  • The aforementioned support for Intel SGX (Software Guard Extensions) in the virtual machine.
  • On a macOS host with Apple Silicon it will allow HVF acceleration to run AArch64 (ARM 64-bit) guest machines.
  • The high-performance ARM-based Fujitsu A64FX processor will now support QEMU's TCG (Tiny Code Generator).
  • Support for more RISC-V instructions, support for SiFive PWM, and other enhancements related to this ISA.
  • Support improvements for IBM POWER10.
  • Intel Snow Ridge v4 issue has been fixed for this version of QEMU.
  • And much more that is waiting for you in this new version ...

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