Libre-SOC, the first open hybrid chip in the CDC 6600 style

The Libre-SOC project unveiled recently have reached the production stage of the first test sample of the OpenPOWER-based open source hybrid CPU / GPU SoC in the style of CDC 6600, in which the CPU, VPU and GPU instructions are not separated and are offered in a single ISA to reduce the size and the complexity of the chip.

This is the first fully independent Power ISA ASIC outside of IBM which becomes Silicon in 12 years, as ellMicrowatt switched to Skywater 130nm in March; however, it is also developed by IBM, as an exceptionally well-made reference design that Libre-SOC used for verification.

The project was originally developed under the name Libre RISC-V, but it was renamed Libre-SOC after the decision to replace RISC-V with OpenPOWER 3.0 Instruction Set Architecture (ISA).

The development of Libre-SOC was funded by the NLnet Foundation, which allocated 400 thousand euros to create a completely open chip cAs part of a program to create verifiable and reliable foundational technical solutions. The chip is 5.5 × 5.9mm in size and includes 130 logic gates.

EThe project aims to create a complete, totally open and royalty-free system on a chip (SoC) that can be used in single board computers, netbooks, and various portable devices. In addition to CPU-specific instructions and general-purpose registers, Libre-SOC provides in a single processor functional block the capabilities to perform vector operations and specialized computations inherent in the VPU and GPU.

The chip uses the OpenPOWER instruction set architecture, the Simple-V extension with instructions to vectorize and process data in parallel, as well as specialized instructions to convert to ARGB and perform typical 3D operations.

"We developed this ASIC on the Power architecture due to its supercomputing pedigree and the decades-long commitment and stability that IBM and other members of the OpenPOWER Foundation have maintained," he said. Luke Kenneth Casson Leighton , Lead Developer and Project Coordinator for Libre-SOC. "On this solid foundation, we can build a reliable and efficient hybrid 3D CPU-VPU-GPU, and our next test ASIC will include Draft Cray-style vector extensions, SVP64."

The GPU instructions focus on use with the Vulkan Graphics API and the VPU in accelerating YUV-RGB conversion and decoding of MPEG1 / 2, MPEG4 ASP (xvid), H.264, H.265, VP8, VP9, ​​AV1, MP3, AC3, Vorbis and Opus formats.

Besides that a free Mesa driver is being developed that uses Libre-SOC capabilities to provide a hardware-accelerated software implementation of the Vulkan graphics API. For example, Vulkan shaders can be JIT translated for execution using specialized instructions available from Libre-SOC.

In the next test prototype, they plan to implement the SVP64 extension (Variable length vectorization), which allows to use Libre-SOC as a vector processor (in addition to 32 general purpose registers of 64 bits, 128 registers for vector calculations will be provided). The first prototype includes only one core, operating at a frequency of 300 Mhz, but within two years it is planned to launch a 4-core version, then an 8-core version and, in the long term, a 64-core version.

The first batch of the chip will be manufactured at TSMC using 180nm process technology. All project developments are distributed under free licenses, including files in GDS-II format with a description of the complete chip topology, enough to start our own production. The Libre-SOC will be the first fully independent chip not based on IBM Power.

The development used the nMigen hardware description language (Python-based HDL, without using VHDL and Verilog), the FlexLib standard cell library from the Chips4Makers project, and the free VLSI Coriolis2 toolkit to convert from HDL to GDS-II.

Finally for those interested in knowing more about it, you can check the details of the project on their official website or for those who are interested in the source code can consult this from the link below.


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