The project recently LLVM announced the release of the new version of the compiler HPVM 2.0 (Heterogeneous Parallel Virtual Machine), whose goal is to simplify programming for systems and provide tools to generate code for domain-specific CPUs, GPUs, FPGAs, and hardware accelerators.
Programming heterogeneous parallel systems is complicated due to the presence in a system of components that use different models to achieve parallelism (CPU cores, vector instructions, GPUs, etc.), different instruction sets, and different memory hierarchies. Each system uses its own combination of these components.
The main idea of the HPVM project is to use a unified representation of parallel executable programs when compiling, which can be used for various types of hardware that support parallel computing, including GPUs, vector instructions, multi-core processors, FPGAs, and various specialized accelerator chips.
Unlike other systems, HPVM tried to combine three possibilities to organize heterogeneous computing: an intermediate representation (IR), a virtual instruction set architecture (V-ISA), and runtime programming, regardless of programming language and hardware.
The HPVM intermediate representation extends the intermediate representation of LLVM instructions by using a hierarchical data flow graph to capture parallelism at the level of tasks, data, and computational pipelines. The HPVM intermediate representation also includes vector instructions and shared memory. The main goal of using an intermediate representation is efficient code generation and optimization for heterogeneous systems.
Virtual Instruction Set Architecture (V-ISA) abstracts low-level hardware and unifies various forms of parallelism and memory architectures using only the underlying concurrency model, the data flow graph.
V-ISA allows portability between different types of hardware for parallel computing and makes it possible not to lose performance when using different elements of heterogeneous systems. Virtual ISA can also be used to deliver generic program executable code that can be run on CPUs, GPUs, FPGAs, and various accelerators.
Flexible compute scheduling policies are applied at runtime and implemented based on information about the program (graphical structure) and by compiling individual program nodes for execution on any of the available target computing devices in the system.
The code generators developed by the project are capable of translating application nodes defined by virtual ISA to run on NVIDIA GPUs (cuDNN and OpenCL), Intel AVX vector instructions, FPGAs, and x86 multicore CPUs. It is noted that the output performance of the HPVM translators is comparable to hand-written OpenCL code for GPU and vector computing devices.
Main new features of HPVM 2.0
For the part of the novelties that are presented In this new version, the following stand out:
- The Hetero-C++ language frontend is proposed, which simplifies the parallelization of the application code in C/C++ languages for compilation in HPVM. Hetero-C++ defines extensions for data level parallelism and hierarchical tasks that map to HPVM thread graphs.
- An FPGA backend has been added to support running code on an Intel FPGA. To orchestrate the execution, the Intel FPGA SDK for OpenCL is used.
- The DSE (Design Space Exploration) framework has been added, which includes compiler optimizations and bottleneck detection mechanisms to automatically tune applications for a given hardware platform.
- The framework contains an out-of-the-box performance model for Intel FPGAs and allows you to connect your own processors to optimize any HPVM-enabled device.
- Optimizations can be applied at both the HPVM dataflow graph level and the LLVM level.
- Updated LLVM components to version 13.0.
- The code has been reorganized to make it easier to navigate through the code base, libraries, and utilities.
- Infrastructure for testing has been improved, new tests have been added for various HPVM components.
Finally, If you are interested in learning more about HPVM, you can check the details in the following link.