CoreBoot 4.16 arrives with support for 33 new boards and more

Few days ago the release of the CoreBoot 4.16 project was announced, in which about 170 developers participated in the creation of the new version and who prepared 1770 changes.

For those who are unfamiliar with CoreBoot, you should know that this is an open source alternative to the traditional Basic I / O System (BIOS) that was already on MS-DOS 80s PCs and replacing it with UEFI (Unified Extensible). CoreBoot is also a free proprietary firmware analog and is available for full verification and auditing. CoreBoot is used as the base firmware for hardware initialization and boot coordination.

Including graphics chip initialization, PCIe, SATA, USB, RS232. At the same time, the binary FSP 2.0 (Intel Firmware Support Package) components and the binary firmware for the Intel ME subsystem, which are required to initialize and launch the CPU and chipset, are integrated into CoreBoot.

Main new features of CoreBoot 4.16

In this new version that is presented, it is highlighted that support for 33 motherboards was added, 22 of which are used in Chrome OS devices or Google servers.

Among the plates that received support and that are not from Google, we can find the following

  • Acer Aspire VN7-572G
  • amd chausie
  • ASROCK H77 Pro4-M
  • ASUS P8Z77-M
  • QEMU power9 emulation
  • Intel Alderlake-N RVP
  • prodrive atlas
  • Star Labs Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)
  • System76 gaze16 3050, 3060 and 3060-b

Furthermore, we can find thatAdded option to disable IME subsystem (Intel Management Engine), which comes with most modern motherboards with Intel processors and is implemented as a separate microprocessor that works independently of the CPU and performs tasks that should be separated from the operating system. Such as the processing of protected content (DRM), the implementation of modules TPM (Trusted Platform Module) and low-level interfaces for equipment monitoring and control.

To disable IME on systems with processors from the Skylake family to Alder Lake, use the me_state parameter in the CMOS, assigning a value of 1 to which will disable the engine. To change the CSME state via CMOS, the ".enable" method has been added, whose state corresponds to the me_state parameter.

Another of the changes that stands out in this new version is that added coreboot-configurator, a Simple GUI to change CMOS settings in Coreboot CBFS using the nvramtool utility.

We can also find that added apcb_v3_edit utility to edit binary files APCB V3 (AMD PSP Customization Block) and replace them with up to 16 SPD (Serial Presence Detect).

The amd_blobs, arm-trusted-firmware, blobs, chromeec, intel-microcode, qc_blobs, and vboot submodules have been updated and the code to configure LAPIC (Local Advanced Programmable Interrupt Controller) has been moved to MP init.

On the other hand, it is highlighted that added support for ANSI escape sequences to highlight important events such as errors and warnings when logging into the interactive console and that the cbmem_dump_console function, similar to cbmem_dump_console_to_uart, but works with normally configured consoles, has been implemented.

Of the other changes that stand out from this new version:

  • Removed support for Google Corsola, Nasher, and Stryke motherboards.
  • Added support for Power9 CPU and AMD Sabrina SoC.
  • Live image settings adapted to work with the NixOS 21.11 distribution. The iasl package has been deprecated and has been replaced by acpica-tools.
  • The U-Boot bootloader has been updated to version 2021.10.
  • Added support for systems with more than 128 CPU cores.
  • Added driver for Semtech sx9360 SAR proximity sensors used in Samsung devices.
  • Added driver for SD SGenesys Logic GL9750 drivers used in
  • Chromebooks.
  • Added support for Realtek RT8125 Ethernet controllers.
  • Added driver for Fibocom 5G WWAN ACPI.
  • Added support for mixed memory topologies when using DDR4.
  • Added support for the FSP 2.3 (Flexible Software Package) specification.
  • Redesigned code for the calculation of hashes used in the verification and evaluation of the state of CBFS
  • Added support for PCI-e Resizable BAR (Base Address Registers) technology, which allows the CPU to access all of a PCI card's video memory.

In addition, a transition plan is provided from version 4.18 to the fourth edition of the resource allocation mechanism (RESOURCE_ALLOCATOR_V4), which adds support for manipulating multiple resource ranges, using the entire address space, and allocating memory in higher areas. to 4GB.

In the release of Coreboot 4.18, expected in November, it is also planned to deprecate the classic multiprocessor initialization mechanism (LEGACY_SMP_INIT), which was replaced by the PARALLEL_MP initialization code.

If you are interested in knowing more about this new version, you can consult the details In the following link.

Get CoreBoot

Finally, for those interested in being able to obtain this new version of CoreBoot they can do it from their download section, which can be found on the official website of the project.

In addition to that in it they will be able to find documentation and more information about the project.

The link is this.


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